Nat. Commun .: New use of electrode

Research Background

Two-dimensional ( 2D) semiconductors have attracted wide attention as ultra-thin channel materials for transistors. The thin nature of the atoms and the free surface without dangling bonds provide huge potential for transistor scaling, which is critical for reducing off-state power consumption and further expanding Moore‘s Law. To date, the main challenges of 2D transistors are the uncontrollable device polarity (n-type or p-type) and the majority carrier type, which poses a critical limitation for implementing complementary CMOS logic functions in 2D transistors. In modern silicon microelectronics, the doping concentration of the silicon channel and the polarity of the transistor are achieved by introducing high-energy ion implantation and subsequent high-temperature activation to introduce extrinsic doping atoms. However, it is not easy to apply this method to 2D semiconductors, because in this thin atomic lattice, the physical space for impurity doping is very small. Therefore, most carrier types of 2D transistors are limited by their inherent characteristics.

In the past few years, great efforts have been made to realize 2D CMOS functions. Early attempts focused on the use of two different 2D semiconductors, one of which is used for NMOS (such as MoS 2 and MoSe 2 ) and the other is used for PMOS (such as black phosphorus and WSe 2 ). Although it can demonstrate the required logic functions, this method still relies on uncontrollable intrinsic doping and is not compatible with CMOS processes. It is also possible to achieve the selective doping of 2D semiconductors through chemical surface adsorption by performing a charge transfer process between the 2D semiconductor and the adsorbate, which can effectively adjust the 2D carrier concentration and the majority carrier type (electron or Void). However, due to the weak interaction between surface doping and 2D materials, this chemical adsorption method is generally less stable. Recently, metals with different work functions have also been used to demonstrate CMOS logic functions in 2D channels. However, due to the strong Fermi level pinning effect, no matter what metal work function is used, a large Schottky barrier is usually observed in the 2D / metal interface.

Achievement introduction

In view of this, recently, Professor Liu Yuan of Hunan University, Professor Duan Fengfeng of the University of California, Los Angeles, and Professor Feng Liping (co-corresponding author) of Northwestern Polytechnical University (co-corresponding author) reported a non-doping strategy using the same contact metal but using different Integrated method to modulate the polarity of WSe 2 transistors . Through the low-energy van der Waals integration of the Au electrode, stable and optimized p-type transistor performance was observed, which is in stark contrast to the transistor prepared using the conventionally deposited Au contact with obvious n-type characteristics on the same WSe 2 wafer . By switching the majority carrier type and achieving the best contact between electrons and holes, an undoped logic inverter is shown with a high voltage gain of 340 at a bias voltage of 5.5 V. In addition, this article also extends the simple polarity control method to achieve more complex logic functions, such as NAND and NOR. The article was published in the famous journal Nature Communications with the title " Doping-free complementary WSe 2 circuit via van der Waals metal integration " .

Graphic guide

Figure 1. Schematic diagram of the device structure and electrical testing. (Ac) The process of preparing WSe 2 transistors using the vdW integrated process: peeling the WSe 2 sheet onto the Si / SiO 2 substrate; the pre-made Au electrode is physically laminated on the WSe 2 surface with weak vdW interaction . ( D) A schematic cross-sectional view of contact with WSe 2 vdW, indicating that the interface is clean and sharp. (E) Evaporate the Au electrode on WSe 2 using conventional thermal evaporation . (F) A schematic cross-sectional view of the evaporation contact with WSe 2 indicating that the interface is highly disordered. ( G) Optical image of the device. (H & i) I ds -V gs transfer characteristics of WSe 2 transistors using vdW integration and conventional evaporation electrodes . By controlling the metal integration method, the device polarity can be switched between p-type and n-type, and the carrier mobility is 16 and 11 cm ² V ^-1 s ^-1 (biased at 1 V).

Figures 1a-f schematically show the device structure. To prepare the device, first, multiple layers of WSe 2 sheets with various thicknesses were mechanically peeled onto a heavily doped silicon substrate (as a gate) with 300 nm silicon oxide (as a gate dielectric). Next, 50 nm Au electrode pairs were prefabricated on Si wafers, and then mechanically released using previously developed methods. The released metal electrodes were aligned under the microscope and physically laminated on top of the WSe 2 sheet using the vdW metal integration process , resulting in an atomically sharp and clean Au / WSe 2 interface (Figure 1a-d). For comparison, another pair of gold electrodes with the same thickness ( 50 nm) were deposited on the same WSe 2 wafer using conventional electron beam lithography , and then subjected to high vacuum thermal deposition, which would lead to diffusion, defects, chemical bonds And strained non-ideal metal / semiconductor interface, as shown in Figure 1e and f. The optical image of the device is shown in Figure 1g, where the left electrode pair is prepared by thermal evaporation, and the right electrode pair is vdW integrated. At room temperature, the electrical transport of the device was studied in vacuum. As shown in Figure 1h, the device in contact with the vdW metal electrode (approximately 7 nm) exhibits p-type I ds -V gs transfer characteristics, which is consistent with the energy band arrangement of WSe 2 and high work function Au, indicating the use of the vdW metal integration method The Au / WSe 2 interface can be optimized . On the contrary, without any doping process, the conventionally depositedThe n-type I ds -V gs transfer characteristics were observed in Au-contacted devices (Figure 1i). The observed change in polarity indicates that the Fermi level pinning effect is strong in the evaporated Au / WSe 2 interface, where the pinned Fermi level is located near the conduction band of WSe 2 . The hole and electron mobility extracted from the device were 16 and 11 cm ² V ^-1 s ^{-1, respectively} .

Figure 2. Thickness-dependent electrical measurements of WSe 2 transistors with vdW integrated and evaporated Au electrodes . ( AC) using vdW Au electrodes, different thickness (3L, 7L and 12L) WSe 2 of the I DS -V GS transfer curve, which is observed from the p-type behavior. Au electrode (DF) using conventional deposition of different thickness (3L, 7L and 12L) WSe 2I ds -V gs transfer curve, respectively observed p-type, bipolar and n-type behavior. (G) the I -50 V and the I 50V current ratio as between WSe 2 function of thickness. For devices with vdW electrodes, a large I -50V / I 50V ratio > 10 ^{3 was} observed , which indicates that the p-type behavior is consistent regardless of the channel thickness . For a conventional device having an Au electrode is deposited, as the thickness of the I -50 V / the I 50V is reduced, which can be clearly seen from the change p-type to n-type.

In order to further confirm the stability of this electrical behavior and study the polarity control through the use of different metal integration processes, various thicknesses of WSe 2Detailed electrical measurements were made. As shown in Figure 2a-c, regardless of WSe 2What is the thickness of the device, the devices in contact with the vdW metal electrode show obvious p-type behavior, and WSe 2The energy bands between the valence band (from a single layer to the block 5.02-4.83 eV) and the high work function Au (5.24 eV) are aligned. In sharp contrast, the contrast device (in contact with the conventionally evaporated Au electrode) with WSe 2The increase in thickness exhibits a unique polarity change behavior, demonstrating p-type characteristics with a thickness of less than 5 layers (~ 3 nm), bipolar characteristics with a thickness of 7 layers (~ 4.5 nm) and thicknesses greater than 10 layers (~ 6.5 nm) n-type characteristics, as shown in Figure 2d-f.

In addition, in order to confirm the stability of this behavior and quantitatively analyze the polarity change, more than 20 devices were measured , and I -50V ( I ds at V g = -50 V ) and I 50V ( V g = 50 V were extracted I ds ) at the time as a function of WSe 2 thickness. The ratio of I -50V / I 50V here can represent the ratio between the hole and electron contribution in a given transistor, so the polarity of the transistor and the majority carrier type can be quantitatively proven. For devices with vdW contact electrodes, when WSe 2 is from a single layer to 30 nm (about 50 layers) thick, an I -50V / I 50V ratio of more than ¹⁰³ is always observed , indicating that regardless of thickness, p-type behavior always accounts for Dominant position (electronic current is negligible). In contrast, for devices with conventional evaporated electrode contacts, as the thickness increases from a single layer to ~ 50 layers, the I -50V / I 50V ratio10 ⁴ drops to ~ 10 ^-3 ( 7 orders of magnitude), which indicates that most carrier types can gradually change from holes to electrons by increasing the thickness of WSe 2 . The I -50V / I 50V V ratio for evaporative contacts (thickness > 13 nm) increases slightly, which can be attributed to the increase in vertical resistance (below the contact area) with increasing thickness.

Figure 3. DFT calculation of Au / WSe 2 interface with different contact methods . (A & b) Au / WSe 2A schematic cross-sectional view of a non-close contact model and a close contact model. ( C) For the non-close contact model, different thicknesses (under Au contact) are calculated. WSe 2Band structure. ( D) For non-close contact models, calculate SBH with WSe 2The change in the number of layers has always been observed to be dominated by p-type SBH in this model . (E) For the intimate contact model, different thicknesses (under Au contact) are calculated WSe 2Band structure. ( F) For the close contact model, calculate SBH with WSe 2The change in the number of layers significantly transitions from p-type SBH to n-type SBH as the layer thickness increases .

In order to further understand the mechanism of using different metal integration methods for polarity control and further study the thickness dependence of the transition from PMOS to NMOS, DFT simulation of carrier transport on the metal / WSe 2 interface was performed . First, two types of Au / WSe 2 were constructedInterface model: the close contact model corresponding to the evaporative Au interface and the non-close contact model corresponding to the vdW integrated Au interface For close contact models, the metal and WSe 2A 1.5 Å interlayer distance (covalent radius of Au and Se) was chosen between them, at which Au and Se atoms were covalently bonded. For the non-intimate contact model, the interlayer distance used is 3.3 Å, in which the vdW gap distance of 1.8 Å is added to the intimate contact layer distance. Based on this model, there are three interfaces that may cause transport barriers: Au and the first layer WSe 2(Interface I), contact WSe 2 below and inside the channel area (Interface II)And the first floor WSe 2And the rest of WSe 2Layer (interface III), as shown in Figures 3a and b.

For non-intimate contact, since the interlayer distance of Au / WSe 2 is large enough and their interlayer interaction is weak, the Au electrode pair WSe 2The performance impact is minimal. WSe 2The interface gap state in the system is negligible, and the entire multilayer WSe 2Maintain its characterizing characteristics, resulting in ohmic contact at interfaces II and III. Therefore, regardless of WSe 2What is the thickness of the contact Schottky barrier exists only in the interface I. Figure 3c showsWSe 2 under vdW Au contactThe calculated energy band structure further shows that the Au electrode and WSe 2 belowWeak interactions. The calculation result of SBH is shown in Figure 3d, in which the p-type Schottky barrier is the main one, which is consistent with the behavior of the p-type transistor observed using vdW Au contact (Figure 2a-c).

In sharp contrast, for the close-contact model, there is a chemical interaction between the Au electrode and WSe 2 , which strongly interferes with the electrical performance of WSe 2 . In WSe 2 forbidden band will generate a large amount of interface states, resulting in WSe 2 bandgap disappear. Therefore, as shown in FIG. 3b, the first layer WSe 2 is metalized under the contact (with a new work function ~ 4.83 eV), thereby forming an ohmic contact at the interface I. At the same time, the charge from metallized WSe 2Transport to semiconductor WSe 2During the process, Schottky barriers were generated at the interfaces II and III. For the single-layer WSe 2 , the lateral Schottky barrier at the interface II is p-type, and the barrier height is 0.19 eV. On the other hand, for multi-layer WSe 2 , the first layer WSe 2 is metallized, but the remaining layers remain largely intrinsic, so the influence of the Schottky barrier at interface III becomes more and more obvious. As shown in Figures 3e and f, when the Au electrode is connected to 3 layers and 5 layers WSe 2At the time of contact, the vertical Schottky barrier at interface III is calculated as p-type, and gradually turns into 7-layer and 9-layer WSe 2The n-type at the time is consistent with the measurement results in Figure 2d-g. Figure 3f shows the change of SBH at interface III with the number of layers.

Figure 4. CMOS logic functions of WSe 2 transistors based on different contact methods . (A) The circuit diagram and optical image of a typical complementary inverter, consisting of two WSe 2 transistors in series , one of which is in contact with the deposited Au electrode (n-type) and the other is in contact with the vdW Au electrode (p-type). (B) The voltage transmission characteristics of the inverter vary with the input voltage. (C) The corresponding voltage gain of the obtained inverter. (D) The bistable hysteresis voltage transfer characteristic of the WSe 2 CMOS logic inverter changes with the input voltage (V dd = 2.5 V), achieving a low noise tolerance (NML) of 1.16 V and a high noise tolerance of 1.19 V Limit (NMH). (E) The relationship between the total noise margin and V dd . ( F) NAND and NOR circuit diagram composed of four WSe 2 transistors , two of which are in contact with the deposited Au electrode as an n-type device, and the other two are in contact with the vdW electrode (p-type). (G & h) Input-output logic function of NAND and NOR circuits.

By controlling the polarity of the transistors, multiple WSe 2 transistors can be easily integrated into the functional circuit. For example, a complementary logic inverter can be implemented by connecting two WSe 2 transistors in series , where one device is in contact with the deposited Au electrode as an n-type device and the other device is in contact with the vdW Au electrode as a p-type device. The logic diagram and optical image of the inverter are shown in Figure 4a, except that the back gate dielectric was changed from 300 nm thick SiO 2 to 20 nm thick Al 2 O 3 to enhance the gate capacitance and electrostatic control of the channel. This is essential for reducing the inverter input voltage and increasing the voltage gain.

Figure 4b shows the relationship between the voltage transfer characteristics of the resulting inverter and the input voltage. The bias voltage (V dd ) is 1.5 to 5.5 V, demonstrating the sharp change with the input voltage. The resulting voltage gain is plotted in Figure 4c, with a peak value of 340 at V dd = 5.5 V, which is the highest value of the TMD-based inverter. Further increase in V dd will cause the gate leakage current to increase greatly and reduce the overall device performance. The higher voltage gain obtained here can be largely attributed to the optimization of PMOS and NMOS contact by controlling their Fermi level position , which is essentially different from the method of evaporating metals with different work functions In the previous method, due to the strong Fermi level pinning effect on the metal / 2D interface, it is difficult to achieve optimal contact with PMOS and NMOS. To characterize the stability of inverters prepared by different contact methods, noise margins ( NML and NMH) were extracted , as shown in Figure 4d. When V dd is 2.5 V, NML of 1.16 V and NMH of 1.19 V are realized. In addition, the relationship between the total noise margin and V dd is also plotted (Figure 4e). Under various bias voltages, the total noise margin measured by the inverter is greater than 90%, indicating a high tolerance to noise .

Furthermore, by connecting more WSe 2 transistors together, more complex logic functions can be realized. For example, four multi-layer WSe 2 can be usedThe transistor builds a logical NOR or NAND function, as shown in the circuit diagram of Figure 4f. The measured input and output voltages clearly demonstrate the logic functions required by NOR and NAND (Figures 4g and h), demonstrating their potential for use in more complex circuits.

Summary and outlook

This article shows an undoped strategy that uses the same contact metal Au and the same channel material WSe 2 , but uses different metal integration methods to control the polarity of 2D transistors. Through detailed thickness-dependent measurements and DFT calculations, it was found that the unique polarity change may be due to the controlled Fermi level pinning (or de-pinning) effect using different metal integration methods. In addition, through optimized contact with PMOS and NMOS, a logic inverter was shown with a maximum voltage gain of 340 (at V dd of 5.5 V), a total noise margin of more than 90%, and more complex CMOS functions For example, NAND and NOR. The results of this paper not only demonstrate high-performance CMOS logic circuits, but also provide a method of using the same contact metal to control the polarity of 2D semiconductors, thus providing ideas for high-performance 2D electronic devices and CMOS design.

Literature information

Doping-free complementary WSe 2 circuit via van der Waals metal integration

( Nat. Commun. , 2020, DOI: 10.1038 / s41467-020-15776-x)

Literature link: https://www.nature.com/articles/s41467-020-15776-x

Source of information: Low Viang

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